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Wiley Encyclopedia of Electrical and Electronics Engineering. Copyright # 1999 John Wiley & Sons, Inc. 294 BiCMOS MEMORY CIRCUITS Vdd Vdd In Vdd Vdd gnd In Out Out gnd gnd CMOS gnd gnd BiCMOS Vdd three-level series-gated ECL and CMOS circuits can directly share supplies. However, the ECL-to-CMOS level conversion is slow because of the large voltage gain required. 3 V CMOS generation, the ECL circuits must be limited to a modified two-level series-gated approach. 3 V CMOS is possible, with the lower voltage either supplied externally or generated internally.

An overflow output pin flags arithmetic operations that exceed the available 2’s complement number range. This pin is logically the exclusive-OR of the carry-output pins Cn and CnϪ1 of an n-bit parallel adder. At the most significant end of the adder, this pin indicates that the result of an arithmetic 2’s complement operation has overflowed into the sign bit, causing the sign bit to become erroneous. If the information is retrieved earlier, the carry bits from the leftmost bit of R(m) could be propagated to the most significant bits immediately, instead of propagating through the buffer cells.

Word-Line Decoder/Driver Because of the large number of rows in a modern SRAM, the word-line decoder must be fast yet low-power. For a BiCMOS Vdd Vdd Vdd R2 SRAM with an ECL front end, the word-line decoder integrates an ECL–CMOS converter and a high-current-gain driver. , they contain no ECL–CMOS converter) and are directly based on a given BiCMOS circuit family, such as the ones shown in Fig. 1 (12,9). Since the bit lines must be driven to CMOS levels to write the SRAM, the write decoder/driver circuitry uses the same circuit techniques as the word-line decoder/driver.

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